1. Field of the Invention
The present invention relates to a slew rate controlling method and system for output data, and more particularly to the slew rate controlling method and system for output data to be performed based on a result from comparison of a potential difference between two power supplies, one being a power supply (VDDQ) to be used for outputting in an output buffer and another being a power supply (VDD) to be used internally in circuits placed in a front stage in an SDRAM (Synchronous Dynamic Random Access Memory) or a like.
The present application claims priority of Japanese Patent Application No. 2002-298009 filed on Oct. 10, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
In order for data being output from an output buffer such as an SDRAM or a like to be correctly recognized by a receiving part, it is necessary that a noise margin is high and that a proportion of a period (valid period) of holding significant data is large and as a concept to show this degree, a data window is used. Also, in order for a valid period to become longer, it is necessary that output data has a balance between its high and low levels and that a slope of a transition portion is large. Generally, when skew between a data strobe signal (DQS) and a data output (DQ) is smaller, the data window becomes the better.
Controlling of a slew rate of data to lengthen a valid period of output data is effective in improving a data window. Conventionally, such controlling of a slew rate of data, in general, is performed in a predetermined fixed manner and in accordance with external setting. (Though a survey on a prior art is carried out in ordinary effort ranges, no information about a reference concretely describing contents of the related art described above was obtained).
However, a valid period of output data varies due to factors related to other devices such as change in a power-supply voltage. For example, if a change occurs in a potential difference between the power supply (VDDQ) to be used for outputting to supply power to an output buffer which produces output data and the power supply (VDD) to be used internally to supply power to circuits placed in a front stage of the output buffer, a valid period of output data becomes short.
That is, there is a problem that, in a device having two types of power supplies in including the power supply to be used for outputting and the power supply to be used internally, or two or more types power supplies, when a potential difference being different from an initial potential difference occurs between the power supply to be used for outputting and the power supply to be used internally due to intrinsic or extrinsic factors during operations, the data window of an output is worsened due to no slew rate control (or speed control) based on proper setting in a state where the potential difference has occurred.